1. Field of the Invention
The invention relates generally to a circuit for clamping a word line voltage. More particularly to The invention relates is concerned with a circuit for clamping a word line voltage for use in devices driven by a high voltage and flash memory cells, which can generate a pumping voltage of a stable potential even in variations in the power supply voltage in the process of pumping the power supply voltage.
2. Description of the Prior Art
Generally speaking, flash memory cells or specific devices are driven by higher voltage than a general power supply voltage. This higher voltage is generated by a pumping circuit and is controlled by a clamping circuit so that it can maintain a constant potential.
Referring now to FIG. 1, an operation of a conventional word line voltage clamping circuit will be below described.
As shown in FIG. 1, the conventional word line voltage clamping circuit includes a pumping signal generating means 110 for generating a pumping signal KICK to a pumping node Q11 according to a first external signal CE; a pre-charging means 120 for pre-charging an output terminal; a first switching means N11 for discharging the pumping node according to a second external signal ATD; a boosting capacitor Cb connected between the pumping node and the output terminal, which increases the potential of the output terminal by a coupling effect of a capacitor to generate the boosting voltage Vboot if the pumping signal KICK is applied; a reference voltage generating means 130 for generating a reference voltage according to the first external signal CE); and a clamping means 140 for comparing the reference voltage and the potential of the pumping node to adjust the potential of the pumping node.
The pumping signal generating means 110 includes an inverter I11 for inverting the first external signal CE, a second switching means P11 for switching the power supply voltage VDD according to the output signal of the inverter I11, and first and second resistors R11 and R12 for dividing the power supply voltage VDD into given voltages, wherein the divided voltages are outputted to the pumping node Q11 as the pumping signal KICK.
The clamping means 140 includes a comparator 141 for comparing the reference voltage and the potential of the pumping node, a third switching means P12 for switching the power supply voltage VDD to the pumping node Q11 according to the output signal of the comparator 141, and a fourth switching means P13 for switching the power supply voltage VDD to the pumping node Q11 depending on an output signal of an Exclusive NOR gate I12 and Exclusive NOR gate I12 using the output signal of the comparator 141 and the second external signal ATD as an input signal. At this time, the driving capability of the fourth switching means P13 is higher than that of the third switching means P12.
In the above, the pumping signal generating means 110, the pre-charging means 120 and the boosting capacitor Cb correspond to a basic construction of the bootstrap circuit which pumps the power supply voltage to produce a high voltage. In order to drive the bootstrap circuit, they receive a chip enable signal and an address transition detection signal. The first external signal CE corresponds to the chip enable signal and the second external signal ATD corresponds to the address transition detection signal ATD. If the first external signal CE is applied, the address signal input is allowed and the second external signal ATD is started to generate.
First, if the first external signal CE is initially applied while the pumping node Q11 maintains a discharging state by the first switching means N11, the discharging state is stopped, the pumping signal KICK is generated in the pumping signal generating means 110 and is then applied to the pumping node Q11, and the reference voltage Vref is then generated in the reference voltage generating means 130. At this time, the pumping signal KICK generated by the pumping signal generating means 110 is lower than a target voltage, applied to the pumping node Q11 and clamped to the target voltage by the clamping means 140.
The comparator 141 in the clamping means 140 compares the reference voltage Vref and the potential of the pumping signal KICK of the pumping node Q11 determine the amount that will be additionally charged to the pumping signal KICK.
In case that the pumping node Q11 must be charged with a small amount of the power supply voltage VDD by applying a high power supply voltage VDD, the comparator 141 generates an output signal of a LOW level to make the third switching means P12 having a low driving capacity an on state. Thus, the pumping node Q11 can be additionally charged with the power supply voltage VDD, so that the potential of the pumping node Q11 can reach the target potential. At this time, the Exclusive NOR gate I12 generates a signal of a HIGH level depending on the output signal of the comparator 141 and the output signal of the pumping node Q11, thus making the fourth switching means P13 an off state.
On the contrary, in case that the pumping node Q11 must be charged with a large amount of the power supply voltage VDD by applying a low power supply voltage VDD, the comparator 141 generates an output signal of a HIGH level to make the third switching means P12. Also, the Exclusive NOR gate I12 generates a signal of a LOW level depending on the output signal of the comparator 141 and the potential of the pumping node Q11, so that the fourth switching means P13 having a high driving capacity has an off state. Therefore, the pumping node Q11 can be additionally charged with a large amount of the power supply voltage VDD so that the potential of the pumping node Q11 can reach the target potential.
Therefore, the clamping means 140 adequately discharges the pumping node Q11 with the power supply voltage VDD through the third or fourth switching means P12 or P13 to generate the pumping signal KICK having the potential of a certain degree that can generate a target boosting voltage Vboot.
In order to generate a constant boosting voltage Vboot even variations in the power supply voltage VDD, this type of the word line voltage clamping circuit must have the comparator 141 being the power supply voltage detection means. In case of the power supply voltage VDD, though the power supply voltage supplier outside a chip supplies a stable power supply voltage VDD, the power supply voltage VDD within the chip is influenced by a bouncing effect due to the power consumption. In particular, loading in order to obtain the boosting voltage Vboot from the output terminal, the timing when detection is made is one that has to drive the boosting capacitor the pumping signal KICK of which has a great. Thus, this timing is sensitive to noise since a lot of power is consumed. Therefore, there is a disadvantage that the power supply voltage VDD detection method is weak to the noise. Also, as detection of the power supply begins after the second external signal ATD is changed from the HIGH level to the LOW level, there is a problem that the operating speed of the device is lowered.
In view of the power consumption of the word line voltage clamping circuit, there is a problem that the power consumption is increased since a current path is always formed.
In the operation of initially discharging the pumping node Q11, there is formed a current path to the second resistor R12 and the switching means N11 through the switching means P11 and the first resistor R11. Thus, there is generated a power consumption.
In the operation of additionally charging the pumping node Q11 with a given power supply voltage in order to generate the boosting voltage Vboot, there is formed a current path to the second resistor R12 of the pumping signal generating means 110 through the third or forth switching means P12 or P13. Thus, there is generated a power consumption.
It is therefore an object of the present invention to provide a circuit for claming a word line voltage capable of minimizing the power consumption and improving the operating speed, in a way that the voltage applied to a triple p-well being a body of a transistor for a voltage fall means is controlled to facilitate a DC operation bias setting, that is, a clamping voltage setting, the clamping operation is performed only when the pumped voltage is higher than a target voltage, and a current path is shielded using the switching means after the clamping operation is finished.
In order to accomplish the above object, a circuit for claming a word line voltage according to the present invention is characterized in that it comprises a reference voltage generating means for generating a reference voltage depending on first and second signals; a bootstrap circuit for generating a pumping voltage of a higher potential than a target voltage depending on the first and second signals to an output terminal; a control signal generating means for generating the first and second control signals depending on the first through third signals; a clamping control means for falling the pumping voltage depending on the first and second control signals to generate a compare voltage; a comparator for comparing the reference voltage and the compare voltage to generate a third signal; and a discharging means for discharging the potential of the output terminal depending on the third signal to fall the pumping voltage to a target voltage.